Method and system for device characterization with array and decoder

ABSTRACT

A system and method for testing devices. The system includes a plurality of pads and a decoder coupled to a plurality of devices. The decoder is configured to receive a plurality of selection signals from the plurality of pads and select a device from the plurality of devices based on at least information associated with the plurality of selection signals. Additionally, the system includes one or more pads connected to the selected device. At least one of the one or more pads is not connected to any of the plurality of devices other than the selected device. The one or more pads are used for testing the selected device.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application is a continuation to U.S. patent application Ser. No.11/339,337, filed Jan. 24, 2006, entitled “Method and System for DeviceCharacterization with Array Decoder” by inventor Gong Bin, which claimspriority to Chinese Patent Application No. 200510111997.5, filed Dec.22, 2005, entitled “Method and System for Device Characterization withArray and Decoder,” by inventor Gong Bin, commonly assigned,incorporated by reference herein for all purposes.

STATEMENT AS TO RIGHTS TO INVENTIONS MADE UNDER FEDERALLY SPONSOREDRESEARCH OR DEVELOPMENT

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REFERENCE TO A “SEQUENCE LISTING,” A TABLE, OR A COMPUTER PROGRAMLISTING APPENDIX SUBMITTED ON A COMPACT DISK

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BACKGROUND OF THE INVENTION

The present invention is directed to integrated circuits. Moreparticularly, the invention provides a method and system for devicecharacterization with array and decoder. Merely by way of example, theinvention has been applied to testing MOS transistors. But it would berecognized that the invention has a much broader range of applicability.

Integrated circuits or “ICs” have evolved from a handful ofinterconnected devices fabricated on a single chip of silicon tomillions of devices. Current ICs provide performance and complexity farbeyond what was originally imagined. In order to achieve improvements incomplexity and circuit density (i.e., the number of devices capable ofbeing packed onto a given chip area), the size of the smallest devicefeature, also known as the device “geometry”, has become smaller witheach generation of ICs. Semiconductor devices are now being fabricatedwith features less than a quarter of a micron across.

Increasing circuit density has not only improved the complexity andperformance of ICs but has also provided lower cost parts to theconsumer. An IC fabrication facility can cost hundreds of millions, oreven billions, of dollars. Each fabrication facility will have a certainthroughput of wafers, and each wafer will have a certain number of ICson it. Therefore, by making the individual devices of an IC smaller,more devices may be fabricated on each wafer, thus increasing the outputof the fabrication facility. Making devices smaller is very challenging,as a given process, device layout, and/or system design often work downto only a certain feature size.

An example of such a limit is characterization of MOS transistors. TheMOS transistors have various gate lengths and gate widths.Conventionally, each transistor is connected to at least one separatepad. For example, each transistor includes four terminals for the gate,the source, the drain, and the substrate respectively, and these fourterminals are connected to four pads respectively. Different transistorsdo not share the same pads. Hence the pad area is much larger than thedevice area. The total area for the pad area and the device area can betoo large.

From the above, it is seen that an improved technique for characterizingMOS transistors is desired.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to integrated circuits. Moreparticularly, the invention provides a method and system for devicecharacterization with array and decoder. Merely by way of example, theinvention has been applied to testing MOS transistors. But it would berecognized that the invention has a much broader range of applicability.

In a specific embodiment, the invention provides a system for testingdevices. The system includes a plurality of pads and a decoder coupledto a plurality of devices. The decoder is configured to receive aplurality of selection signals from the plurality of pads and select adevice from the plurality of devices based on at least informationassociated with the plurality of selection signals. Additionally, thesystem includes one or more pads connected to the selected device. Atleast one of the one or more pads is not connected to any of theplurality of devices other than the selected device. The one or morepads are used for testing the selected device.

According to another embodiment, a system for testing transistorsincludes a plurality of pads and a decoder coupled to a plurality oftransistors. The decoder is configured to receive a plurality ofselection signals from the plurality of pads and select a transistorfrom the plurality of transistors based on at least informationassociated with the plurality of selection signals. Additionally, thesystem includes a first pad connected to a first terminal for theselected transistor, a second pad connected to a second terminal for theselected transistor, a third pad connected to a third terminal for theselected transistor, and a fourth pad connected to a fourth terminal forthe selected transistor. The first pad is not connected to any of theplurality of transistors other than the selected transistor, and thesecond pad is not connected to any of the plurality of transistors otherthan the selected transistor. The first pad, the second pad, the thirdpad, and the fourth pad are used for testing the selected transistor.

According to yet another embodiment, the method for testing devicesincludes receiving a plurality of selection signals, processinginformation associated with the plurality of selection signals, andselecting a device from a plurality of devices based on at leastinformation associated with the plurality of selection signals. Theselected device is coupled to at least a control device. Additionally,the method includes generating a control signal associated with theselected device, receiving the control signal by the control device,connecting the selected device to at least one of one or more pads bythe control device, and testing the selected device with the one or morepads.

Many benefits are achieved by way of the present invention overconventional techniques. Some embodiments of the present inventionprovide a testing mechanism that can significantly reduce the pad areaand/or the total area. For example, the array includes 256 devicessubject to testing. The average area for each device is about 100 μm².Each device uses only one pad for testing. Each pad area is about 6400μm². In a conventional technique, the pad for each device is not sharedwith other devices. The pad area is about 98.5% of the total area.According to certain embodiments of the present invention, the totalnumber of pads can be reduced from 256 to 9. The 9 pads include 8selection pads and 1 test pad. Hence the total pad area is reduced by96.5% in this example. Depending upon the embodiment, one or more ofthese benefits may be achieved. These and other benefits will bedescribed in more detail throughout the present specification and moreparticularly below.

Various additional objects, features and advantages of the presentinvention can be more fully appreciated with reference to the detaileddescription and accompanying drawings that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified system for testing devices according to anembodiment of the present invention;

FIG. 2 is a simplified method for testing devices according to anembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to integrated circuits. Moreparticularly, the invention provides a method and system for devicecharacterization with array and decoder. Merely by way of example, theinvention has been applied to testing MOS transistors. But it would berecognized that the invention has a much broader range of applicability.

FIG. 1 is a simplified system for testing devices according to anembodiment of the present invention. This diagram is merely an example,which should not unduly limit the scope of the claims. One of ordinaryskill in the art would recognize many variations, alternatives, andmodifications. The system 100 includes the following components:

-   1. Selection pads 110;-   2. Decoder 120;-   3. Test pads 130.

Although the above has been shown using a selected group of componentsfor the system 100, there can be many alternatives, modifications, andvariations. For example, some of the components may be expanded and/orcombined. Other components may be inserted to those noted above.Depending upon the embodiment, the arrangement of components may beinterchanged with others replaced. Further details of these componentsare found throughout the present specification and more particularlybelow.

The decoder 120 is coupled to an array 140 for devices subject totesting. The decoder 120 receives selection signals from the selectionpads 110, and in response selects a device from the array 140. Theselected device is connected to the test pads 130, and the other devicesof the array 140 are not connected to all of the test pads 130. Forexample, the array 140 includes MOS transistors, and the selected MOStransistor has four terminals for the gate region, two source/drainregions, and the substrate region. Each terminal of the selected MOStransistor is connected to one of the test pads 130. The test pads 130include four pads, each of which corresponds to a different terminal ofthe selected MOS transistor.

In one embodiment, the array 140 includes a plurality of MOS transistorssubject to testing. One of the plurality of MOS transistors is a MOStransistor 210 including terminals 212, 214, 216, and 218. The test padsinclude pads 250, 252, 254, and 256. The pad 250 is connected to theterminal 212 for the source/drain region, and the pad 252 is connectedto the terminal 214 for the substrate region. The terminal 216 for thegate region is connected to a control transistor 230, and the terminal218 for the source/drain region is connected to a control transistor220. The gates of the control transistors 220 and 230 each receive acontrol signal 240. For example, the transistor 210 is selected by thedecoder 120 in response to selection signals received from the selectionpads 110. In response, the control signal 240 turns on the controltransistors 220 and 230. The terminal 216 for the gate region isconnected to the pad 254, and the terminal 218 for the source/drainregion is connected to the pad 256. In another example, the transistor210 is not selected by the decoder 120 in response to selection signalsreceived from the selection pads 110. In response, the control signal240 turns off the control transistors 220 and 230. The terminal 216 forthe gate region is not connected to the pad 254, and the terminal 218for the source/drain region is not connected to the pad 256.

In another embodiment, the array 140 includes 256 devices subject totesting. The selection pads 110 include 8 pads for the decoder 120 toselect one of the 256 devices on a binary basis. In yet anotherembodiment, the array 140 of devices is replaced by a plurality ofdevices that are not arranged in an array.

FIG. 2 is a simplified method for testing devices according to anembodiment of the present invention. This diagram is merely an example,which should not unduly limit the scope of the claims. One of ordinaryskill in the art would recognize many variations, alternatives, andmodifications. The method 300 includes the following processes:

-   1. Process 310 for receiving selection signals;-   2. Process 320 for selecting a device;-   3. Process 330 for turning on or off control devices;-   4. Process 340 for testing selected device.

Although the above has been shown using a selected group of processesfor the method 300, there can be many alternatives, modifications, andvariations. For example, some of the processes may be expanded and/orcombined. Other processes may be inserted to those noted above. Forexample, the method 300 is performed by the system 100. Depending uponthe embodiment, the arrangement of processes may be interchanged withothers replaced. Further details of these processes are found throughoutthe present specification and more particularly below.

At the process 310, selection signal are received. For example, thedecoder 120 receives selection signals from the selection pads 110. Atthe process 320, a device is selected from a plurality of devices. Forexample, the device 210 is selected from the array 140, and the array140 includes the plurality of devices subject to testing.

At the process 330, control devices for the plurality of devices areturned on or turned off. For example, the array 140 includes theplurality of devices subject to testing. Each of the plurality ofdevices corresponds to at least one control device. In one embodiment,if one of the plurality of devices is selected, the corresponding atleast one control device is turned on in order to connect the selecteddevice to the test pads 130. The control devices corresponding to theother devices of the plurality of devices are turned off in order todisconnect each of the unselected devices from at least one of the testpads 130.

For example, the transistor 210 is selected by the decoder 120 inresponse to selection signals received from the selection pads 110. Inresponse, the control signal 240 turns on the control transistors 220and 230. The terminal 216 for the gate region is connected to the pad254, and the terminal 218 for the source/drain region is connected tothe pad 256. In another example, the transistor 210 is not selected bythe decoder 120 in response to selection signals received from theselection pads 110. In response, the control signal 240 turns off thecontrol transistors 220 and 230. The terminal 216 for the gate region isnot connected to the pad 254, and the terminal 218 for the source/drainregion is not connected to the pad 256.

At the process 340, selected device is tested. In one embodiment, theselected device is the transistor 210. For example, the transistor 210is tested to measure I_(ds) as a function of V_(gs), and/or I_(ds) as afunction of V_(ds). I_(ds) represents current between the twosource/drain regions. V_(gs) represents voltage drop between the gateregion and the source/drain region that functions as the source. V_(ds)represents voltage drop between the two source/drain regions. In anotherexample, the transistor 210 is tested to measure the transistorthreshold voltage V_(t).

According to another embodiment, a system for testing devices includes aplurality of pads and a decoder coupled to a plurality of devices. Thedecoder is configured to receive a plurality of selection signals fromthe plurality of pads and select a device from the plurality of devicesbased on at least information associated with the plurality of selectionsignals. Additionally, the system includes one or more pads connected tothe selected device. At least one of the one or more pads is notconnected to any of the plurality of devices other than the selecteddevice. The one or more pads are used for testing the selected device.For example, the system is implemented according to the system 100.

According to yet another embodiment, a system for testing transistorsincludes a plurality of pads and a decoder coupled to a plurality oftransistors. The decoder is configured to receive a plurality ofselection signals from the plurality of pads and select a transistorfrom the plurality of transistors based on at least informationassociated with the plurality of selection signals. Additionally, thesystem includes a first pad connected to a first terminal for theselected transistor, a second pad connected to a second terminal for theselected transistor, a third pad connected to a third terminal for theselected transistor, and a fourth pad connected to a fourth terminal forthe selected transistor. The first pad is not connected to any of theplurality of transistors other than the selected transistor, and thesecond pad is not connected to any of the plurality of transistors otherthan the selected transistor. The first pad, the second pad, the thirdpad, and the fourth pad are used for testing the selected transistor.For example, the system is implemented according to the system 100.

According to yet another embodiment, the method for testing devicesincludes receiving a plurality of selection signals, processinginformation associated with the plurality of selection signals, andselecting a device from a plurality of devices based on at leastinformation associated with the plurality of selection signals. Theselected device is coupled to at least a control device. Additionally,the method includes generating a control signal associated with theselected device, receiving the control signal by the control device,connecting the selected device to at least one of one or more pads bythe control device, and testing the selected device with the one or morepads. For example, the method is implemented according to the method300.

The present invention has various applications. In one embodiment, thesystem 100 and/or the method 300 are used to characterize devices. Inanother embodiment, the system 100 and/or the method 300 are used toextract parameters for device modeling. For example, the array 140includes a plurality of MOS transistors subject to testing. These MOStransistors are of the same type but with various gate lengths and gatewidths. Each of these MOS transistors is individually selected andtested. The testing results are used to extract characteristicparameters, which can be used for device modeling and/or other purposes.

The present invention has various advantages. Some embodiments of thepresent invention provide a testing mechanism that can significantlyreduce the pad area and/or the total area. For example, the array 140includes 256 devices subject to testing. The average area for eachdevice is about 100 μm². Each device uses only one pad for testing. Eachpad area is about 6400 μm². In a conventional technique, the pad foreach device is not shared with other devices. The pad area is about98.5% of the total area. According to the system 100 and/or the method300, the total number of pads can be reduced from 256 to 9. The 9 padsinclude 8 selection pads and 1 test pad. Hence the total pad area isreduced by 96.5%.

It is also understood that the examples and embodiments described hereinare for illustrative purposes only and that various modifications orchanges in light thereof will be suggested to persons skilled in the artand are to be included within the spirit and purview of this applicationand scope of the appended claims.

1. A system for testing transistors, the system comprising: a pluralityof pads; a plurality of transistors including a first transistor, thefirst transistor including a first terminal, a second terminal, a thirdterminal, and a fourth terminal; a decoder coupled to the plurality oftransistors and configured to receive a plurality of selection signalsfrom the plurality of pads and select the first transistor from theplurality of transistors based on at least information associated withthe plurality of selection signals, the decoder being adapted togenerate a control signal based at least on the selection signals; afirst pad coupled to the first terminal of the first transistor througha second transistor, the first terminal of the first transistor beingeither a source terminal or a drain terminal of the first transistor,the second transistor including a fourth, a fifth, and a sixth terminal,the sixth terminal being configured to receive the control signal fromthe decoder, the first pad being electrically coupled to at most one ofthe plurality of the transistors including the first transistor; asecond pad coupled to the second terminal of the first transistorthrough a third transistor, the third transistor comprising a seventhterminal, a eighth terminal, and a ninth terminal, the second terminalof the second transistor being a gate terminal of the first transistor,the second pad being electrically connected to at most one of theplurality of the transistors including the first transistor; a third padelectrically connected to the third terminal of the first transistor,the third terminal being a substrate terminal of the first transistor;and a fourth pad electrically connected to the fourth terminal of thefirst transistor, the fourth terminal being the source terminal of thefirst transistor if the first terminal is the drain terminal of thefirst transistor, or the drain terminal of the first transistor if thefirst terminal is the source terminal of the first transistor.
 2. Thesystem of claim 1 wherein: the sixth terminal is a gate terminal of thesecond transistor; the ninth terminal is a gate terminal of the thirdtransistor; the fourth terminal and the fifth terminal of the secondtransistor are either a source terminal or a drain terminal of thesecond transistor, the fourth terminal being the drain terminal of thesecond transistor if the fifth terminal is the source terminal of thesecond transistor and the fourth terminal being the source terminal ofthe second transistor if the fifth terminal is the drain terminal of thesecond transistor; and the seventh terminal and the eighth terminal ofthe third transistor are either a source terminal or drain terminal ofthe third transistor, the seventh terminal being the drain terminal ofthe third transistor if the eighth terminal is the source terminal ofthe third transistor and the seventh terminal being the source terminalof the third transistor if the eighth terminal is the drain terminal ofthe third transistor.
 3. The system of claim 1 wherein: the first pad iscoupled to the first terminal of the first transistor further through anelectrical connection between the first pad and the fourth terminal ofthe second transistor and an electrical connection between the fifthterminal of the second transistor and the first terminal of the firsttransistor; and the second pad is coupled to the second terminal of thefirst transistor further through an electrical connection between thesecond pad and the seventh terminal of the third transistor and anelectrical connection between the eighth terminal of the thirdtransistor and the second terminal of the first transistor.
 4. Thesystem of claim 2 wherein the sixth terminal of the second transistorand the ninth terminal of the third transistor are electricallyconnected, and the ninth terminal of the third transistor is adapted toreceive the control signal from the decoder to select the firsttransistor for testing.
 5. The system of claim 1 is further adapted fortesting transistors wherein the plurality of transistors is arranged inan array.
 6. The system of claim 1 wherein the plurality of selectionsignals includes an N number of signals, the control signal beingcapable of selecting the first transistor from up to 2^(N) number oftransistors.
 7. The system of claim 6 wherein N is 8 and the pluralityof transistors consists of 256 transistors.
 8. The system of claim 1wherein the plurality of transistors and MOS transistors.
 9. The systemof claim 1 wherein the control signal selects one transistor at a timefor testing.